Numerous types of consumer electronics products rely on some form of mass storage for retaining data or software for the execution of code by a microcontroller. Such consumer electronics are prolific, and include devices such as personal digital assistants (PDA's), portable music players, portable multimedia players (PMP's) and digital cameras. In PDA's, mass storage is required for storing applications and data, while portable music players and digital cameras require large amounts of mass storage for retaining music file data and/or image data. The mass storage solution for such portable electronics is preferably small in size, consumes minimal power, and has high storage density. This limits the selection to non-volatile forms of memory since volatile memories, such as static random access memory (SRAM) and dynamic random access memory (DRAM), require a constant application of power in order to retain data. As is known in the art, portable electronics rely on batteries that have a finite power supply. Therefore, non-volatile memories that retain data after power is removed are preferred.
While many consumer products use commodity Flash memory, Flash memory is indirectly used by consumers in products such as cell phones and devices with microprocessing functions. More specifically, the application specific integrated circuits (ASIC) commonly found in consumer electronics can have integrated Flash memory to enable firmware upgrades. Needless to say, Flash memory is versatile due to its optimal balance in size, storage density, and speed, making it a preferred non-volatile mass storage solution for consumer electronics.
FIG. 1 is a block diagram of a typical Flash memory device. Flash memory 10 includes logic circuitry for controlling various functions of the Flash circuits, registers for storing address and data, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing the Flash memory array. The functions of the shown circuit blocks of Flash memory 10 should are well known in the art. Persons skilled in the art will understand that Flash memory 10 shown in FIG. 1 represents one possible Flash memory configuration among many possible configurations.
A read operation is a relatively straightforward access of data stored at a particular memory location of the memory array, called an address. Prior to a write operation to a specific block of the memory array, the specific block must first be erased with the application of high voltages. A write operation, more accurately called a program operation, requires the careful application of high voltages to a selected memory location, followed by a program verify operation to ensure that the data has been properly programmed. Furthermore, since high voltages are used, the Flash chip must be designed to be relatively tolerant to inadvertent programming of non-selected memory cells.
FIG. 2 is a circuit schematic showing a NAND cell string used in memory cell array shown in FIG. 1. FIG. 2 is a circuit schematic of two NAND memory cell strings. Each NAND memory cell string includes 32 serially connected floating gate memory cells 50 each connected to respective wordlines WL0 to WL31, a string select transistor 52 connected between the bitline 54 and the first floating gate memory cell 50, and a ground select transistor 56 connected between a common source line (CSL) 58 and the last floating gate memory cell 50. The gate of string select transistor 52 receives a string select signal SSL, while the gate of ground select transistor 56 receives a ground select signal GSL. The NAND memory cell strings of a block share common wordlines, string select SSL, and ground select GSL signal lines. The construction and arrangement of the shown NAND memory string is well known in the art.
As previously mentioned, the NAND memory cell strings of the memory array are first erased, according to well-known techniques in the art. Each block of NAND memory cell strings can be selectively erased; therefore one or more blocks can be simultaneously erased. When successfully erased, all erased floating gate memory cells 50 will have a negative threshold voltage. In effect, all erased memory cells 50 are set to a default logic state, such as a logic “1”, for example. Programmed memory cells 50 will have their threshold voltages changed to a positive threshold voltage, thus representing the opposite “0” logic state.
FIG. 3 is a cross-sectional schematic of a typical Flash memory cell. A structure of such cells in well known in the art. Generally, control gate 60 is connected to a word line, while the floating gate 62 is isolated from all other nodes by an oxide insulator 61. Electrons (charge carriers) are injected into or ejected from floating gate 62 and substrate 68 having a source 64 and a drain 66, through thin tunneling oxide 63 between floating gate 62 and substrate 68.
FIG. 4 is a cross-sectional schematic of a nitride ROM cell having charge traps. Such a cell is also known in the art. In a nitride ROM cell, the floating gate is eliminated and the data is placed in a “holding chamber” or “charge traps” of the non-conductive layer 72, for example, of silicon nitride, between the control gate 70 and substrate 78 having a source 74 and a drain 76. Recently, silicon nanocrystals have also been used as charge traps.
Generally, a cell is programmed by applying a high voltage to its gate while keeping its source and drain terminals grounded. The high electrical field causes electrons in the memory cell channel to cross the gate oxide and embed in the floating gate (known as Fowler-Nordheim (F-N) Tunneling), thereby increasing the effective threshold voltage of the memory cell.
Due to the ever-increasing need for size reduction as well as the desire to increase the density of data storage, multi-level FLASH cells are now being widely used. As the name suggests, multi-level cells have more than two logic states per cell. A single cell storing two bits of information has 4 logic states corresponding to different levels of charge levels stored in the floating gates (or charge traps). Generally, a multi-level cell capable of storing N binary bits of data will have 2N states or logic levels.
However, each floating gate transistor has a certain total range of threshold voltages in which it may practically be operated. The total range is divided into the number of states defined for the memory cell including allowances for clear distinction of one state from another. Variations in fabrication processes and ageing of the device may cause shifts in the threshold voltages. These shifts can weaken the strength of cell states by moving one state closer to the next state. Also, as more levels are squeezed into a fixed total range (for example, fixed supply-voltage range), the tolerance for these shifts decreases.
FIG. 5 is a threshold voltage (Vt) distribution graph for a multi-level Flash memory cell. The intermediate reference voltages are also shown. This particular graph illustrates the thresholds of a Flash memory cell capable of storing 2 bits of data. Therefore, each multi-level Flash memory cell must store one of four threshold voltages. In this prior art scheme, an erased state represented by a negative threshold voltage lies in an erase voltage domain. All erased memory cells will by default have this negative threshold voltage. The remaining three states must be programmed, and their corresponding threshold voltages will be positive in value and lie in the program voltage domain. In this example, the erase voltage domain is below zero while the program voltage domain is above zero volts. A problem with this scheme is the required tightness of the distribution for each state and the distance between the states.
Programming is typically done by the page, meaning that all the memory cells 50 in the block connected to the same wordline are selected to be programmed with write data (logic “0”) at the same time. The remaining memory cells are thus unselected during programming. Since the memory cells start in the erased state (logic “1”) prior to programming, only the memory cells to be programmed with the logic “0” should be subjected to the high electric fields necessary to promote F-N tunneling. However, due to the physical connections of the memory array, all the memory cells along the same wordline receive the same high voltage programming level. As a result, there is a potential that erased memory cells will have their threshold voltages unintentionally shifted. This is called program disturb, which is well known in the Flash memory field. This problem is more pronounced in multi-level cells as more levels are squeezed into a fixed voltage range.
Several parameters such as, Vt window, Vt distance, and Vread distance, are key parameters to determine read/write speed, reliability and lifetime of multi-level flash memory shown in FIG. 5. These three parameters influence one another: the cell Vt window and the cell Vt distance in a multi-level flash memory are much tighter than those in single-level flash memory since, in the case of a 2 bit cell, three cell states are in the program voltage domain with a positive Vt. If the cell Vt window is wider, the cell Vt distance is narrower. This reduces read sensing margin and eventually leads to a failure to sense neighboring cell states. In other words, Vt overlap or even minimum Vt distance between neighboring cell states leads to device failure.
The strength or safety margin of a Vt-state is greatest when the Vt is half-way between adjacent reference voltages. Upper and lower limits for each Vt-state defining a cell Vt window may be specified. For example, in FIG. 5, cell state 0 is between lower limit VL0 (−3 volts) and upper limit VU0 (−2 volts). Cell state 1 is between lower limit VL1 (0.3 volts) and upper limit VU1 (0.8 volts). Typically, the cell Vt window in multi-level flash memory is in between 0.5 to 1.0 volts. Ideally, a narrow cell Vt window is preferred for better definition and distinction of a state.
The cell Vt distance, which is defined as the difference in Vt between the lower limit of Vt of the threshold voltage range of one cell state and the upper limit of Vt of the threshold voltage range of the previous cell state. For example, the Vt distance between cell state 2 and cell state 1 is 1.5−0.8=0.7 volts. Typically the cell Vt distance in a multi-level flash memory cell is in between 0.7 to 1.0V. As is evident, larger cell Vt distances are preferred.
It is also desirable to have the Vread distance, the distance between the read pass voltage and the upper limit of the fully programmed state as high as possible. For example, in FIG. 5, Vread distance is 5.5−3.3=2.2 volts. However, for optimum performance of the memory cell, a lower Vread is preferred as high Vread can cause disturbance. Therefore, there is a trade-off between Vread distance and the value of Vread. Moreover, the fixed supply-voltage range available may determine the maximum Vread value.
Furthermore, as the number of rewrite (erase & program) cycle increases, the cell Vt window becomes wider by tunnel oxide degradation due to trapped charges. Also, the read pass voltage Vread should be lower to minimize read disturbance to unselected cells in the selected string. However, in order to accommodate the three cell states (in 2 bit cell) in the program voltage domain, the Vread distance has to be maintained at least well above VU3. This increases the level of Vread.
In order to tightly control the Vt of the programmed cell, incremental step pulse programming (ISPP) has been proposed and widely used in flash memories. FIG. 6 is a graph illustrating the relationship between the number of program pulses applied to a wordline for programming a threshold voltage versus the size of each pulse. Generally, tight threshold voltage distributions can be obtained when the step size of each program pulse is small. However, the trade-off is programming time since more program pulses would be required.
Accumulated program/erase cycles in multi-level flash memories with the above prior art scheme for cell Vt distribution typically results in well-known problems as described below.
Repeated charge transfer causes electrons to be trapped in the floating gate and the dielectric, which degrades program and erase characteristics of the cells. Consequently, cells require gradually higher program and erase voltages as the number of erase-program cycle increases; resulting in limiting the number of erase-program cycles on a cell.
The data retention characteristic in multi-level cells will be drastically degraded due to a small cell Vt distance. Moreover, as the Vt distribution for a given state is larger, the maximum Vt of programmed cells is higher. The higher Vt requires a higher programming voltage Vpgm, and adversely affects the data retention characteristics due to the larger electric field across the tunnel oxide. Moreover, the higher Vt required in multi-level cells require higher Vread. This causes read disturbance to unselected memory cells in the selected NAND cell string during read operations (i.e. soft-program by higher Vread to unselected memory cells).
In addition, the higher voltage requirements for read and write operations in multi-level flash memory does not scale with device dimension scaling as the electric field across all transistors including memory cells cannot be reduced.
Therefore, the life of a multi-level Flash memory cell is relatively short, typically only 10,000 cycles. This is significantly shorter than the 100,000 cycle limit for single bit per cell Flash memory devices.